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| Examples of state-of-the-art thermal management solutions at the dawn of the 21st century (left to right): a TCM module, a high-density heat sink, and an ultra performance, low profile fan-sink. | ||
Thermal management has served as a key enabling technology in the development of advanced microelectronic systems and has facilitated many of the “Moore’s Law” [Moore, G.E., 1975] advances in consumer products and high-performance computers that have defined the latter part of the 20th century.
The widespread replacement of bipolar IC technology with CMOS IC’s in the late 1980’s produced a short-lived hiatus in the temporal rise of on-chip power dissipation and heat flux. But, as the new century begins, it appears that the announced death of electronic cooling was rather premature and thermal management is again squarely on the critical path in the development process of almost every electronic product category.
While per-gate CMOS switching energy continues to fall, the thirst of the marketplace for greater IC speed and functionality has fueled a recent acceleration in chip power dissipation and thermal requirements. The SIA 1997 Roadmap thus anticipates the use of 1.5GHz, 40M transistor, 385mm2 microprocessor chips dissipating as much as 110W in workstations and servers offered in 2001 and a further substantial increase to 3.5GHz, 200M transistor, 520mm2 chips dissipating 160W for use in the 2006 workstations and servers [SIA,1997].
Under the pressure of these developments, it is thermal management – once again – that frequently defines the limits of performance, functionality, and reliability of electronic systems. Moreover, without enhancements in thermal technology, modeling, and design techniques, it is unlikely that the full potential of future semiconductor device technology could be realized in product performance and cost-effectiveness.
Consequently, “thermal packaging” has become a familiar term in the lexicon of electronic product developers, and recent years have witnessed a proliferation of conferences, books, and journals dealing with this subject. Practitioners of the thermal arts – as they apply to electronic components and systems – are once again in high demand throughout the electronic industry.
History of Thermal Packaging
The 150W chip power dissipation, projected for the middle of the next decade, dwarfs by three orders-of-magnitude the 0.1W to 0.3W typical of small scale integration (SSI) devices used in the early 1960’s, at the dawn of the microelectronic era. Over the next twenty years, chip heat generation increased by just one order of magnitude to approximately 1-5W in the large-scale integration (LSI) bipolar devices and very large scale integration (VLSI) CMOS devices of the mid-1980’s. But, by the early 1990’s, larger, faster CMOS chips pushed power dissipation to the range of 15-30W [Bar-Cohen, A.,1993] and set the stage for the prodigious thermal management needs ahead.
During the past three decades, the successful application of thermal science and insightful thermal optimization have allowed component temperatures to be stabilized at values below 100°C, despite this rapid increase in chip power dissipation and even in the presence of a hostile external environment. But, it is instructive to recall that it was a transformer cooling study by Cockroft in 1925 that first brought thermal management to the attention of the electrical engineering community.
Cockroft’s work was followed, in the 1930’s, by two key papers by Mouromtseff and Koyanowski [1935] and Mourmotseff [1942] dealing with air-and liquid-cooling of high-power vacuum tubes. A classic study by Elenbaas in 1942, addressing the design and optimization of natural convection fin arrays, closed this first era of thermal packaging.
Following World War II, the growing use of electronics in both the military and commercial sectors, led to a widespread recognition of the need for thermal packaging and design of electronic components and to the first flowering of thermal control technology [Kaye, J., 1956]. The systematic implementation of promising concepts, literally conceived in the “heat of battle,” led to extensive evolutionary improvements in vacuum tube cooling, the demonstration of techniques for the enhancement of external convective heat transfer, and the development of liquid cooling, through integral passages, for high-power travelling wave tubes.
Despite the dramatic reduction in power dissipation, made possible by transistor replacement of vacuum tubes, the inverse temperature dependence of transistor efficiency and reliability, as well as the rapidly growing transistor packaging density, considerably expanded the role of the thermal packaging engineer. The development and thermal design of so-called cold-plates, for the mounting and thermal servicing of transistorized components, began to occupy many workers in the field.
Although the scope of electronic cooling applications continued to expand throughout the 1960’s and 1970’s, notably in response to the development of the solid-state transistor [Kilby, 1964], much of the technical effort during these decades was devoted to applying, documenting, and standardizing conventional air- and liquid-cooling techniques [Bergles, et al 1972].
Promising, but more novel, thermal management concepts, including the use of refrigerants, immersion cooling, augmented flow boiling, heat pipes, and thermoelectric devices, languished in the laboratories of the major computer companies, only rarely migrating from “proof-of-concept” studies to actual products.
In the 1980’s growing competitive pressures for higher reliability, quality and computational performance at ever lower prices accelerated the spread of VLSI CMOS semiconductor technology to high-end applications. The relatively low power dissipation of the CMOS IC’s, increasingly in use in the portable, desk-top, and workstation products, contrasted sharply with the high heat flux bipolar components used in the mainframes and supercomputers, leading to a bifurcation in thermal packaging technology.
Attempts to mimic CMOS gate densities, reliability, and cost with bipolar technology required increasingly higher dissipation and structurally-complex single chip packages, as well as sophisticated multichip modules, interconnecting as many as 150 chips across a common substrate.
The increased bipolar power densities, to as much as 7W (15-25W/cm2) at the chip and 300W (2-3W/cm2) at the substrate level, led in the mid-1980’s to the near-universal adoption of large, liquid-cooled, multichip modules for mainframes and supercomputers [Bar-Cohen, A., 1987]. Alternately, cooling of the commonly used, 1-2W, 4MHz CMOS microprocessors could be accomplished with air-cooled heat spreaders and heat sinks, assisted – when needed – by small fans.
Despite relatively primitive implementations, the water-cooled mainframe computers of IBM, Honeywell, and Sperry offered significant improvements in circuit density and heat removal capability relative to previous designs [Lyman, J., 1982]. This success led to broader acceptance of water-cooled multichip modules and the adoption, in the late 1980’s, of more refined indirect liquid cooling designs by IBM, Fujitsu, Hitachi, NEC, Siemens, and other major OEM’s.
A third generation of such modules, capable of handling 2-5kW in a 225-1000cm2 footprint, reached commercial implementation in the early 1990’s [Bar-Cohen, A., 1993]. Recognition that the thermal resistance at the interface between the chip and the package, constrained and often limited the thermal performance of these modules, led the thermal packaging community to vigorously explore direct liquid cooling for the anticipated high power applications [Bergles, A.E. and Bar-Cohen, A, 1990].
Considerable excitement was generated in the early 1980’s by the development of compact heat exchangers and miniature refrigerators etched in silicon, which could be used to integrate the cooling system with the chip [Tuckerman, D. and Pease, F.,1981, and Wu, P. and Little, W.A., 1984, respectively]. Direct liquid cooling of bare chips and chip packages in dielectric liquids, first considered for implementation in the early 1970’s [Oktay, S., 1982], was successfully implemented in two of the leading supercomputers of the late 1980’s.
In the Cray-2, chip modules were immersed in slowly circulating FC-72 [Danielson, R., et al, 1986] and in CDC’s ETA-10, components attached to large printed circuit boards, were chilled by immersion in liquid nitrogen [Vacca, A., et al 1987]. A prototype of the SS-1 supercomputer, unveiled as the 1990’s began, relied on FC-72 jet impingement to remove 95W/cm2 from chips in a multichip module [Ing, P. et al 1993].
Though overshadowed by the more aggressive liquid cooling techniques and constrained by the inherent limitations of a relatively poor coolant, air-cooling technology was undergoing significant evolutionary improvements throughout the 1980’s. This development was most visible in the mid-range computers, such as DEC’s VAX family, IBM’s 4380 family, and the Unisys A-16 product line. These “departmental” computers continued to leverage traditional bipolar IC technology, but shared a growing number of applications and market segments with the low-power, CMOS-based workstations.
Reliance on impingement cooled arrays of pin fins and careful design of the air distribution conduits, along with use of internal heat spreaders and improved interface materials, made it possible for these relatively low-cost, air-cooled multichip modules to approach the spatial and volumetric cooling capability of the water-cooled modules [Bar-Cohen, A. 1987; Bar-Cohen, A. 1993]. These late-1980’s air-cooled modules provided cost-effective thermal packaging solutions for the electronic industry and served as a test bed for concepts and materials that would later emerge to dominate the physical design of computer systems.
State-of-the-Art
The effort to build an industry-wide technology roadmap, begun in 1992 by the Semiconductor Industry Association (SIA) [SIA-1992], made manifest the deeply-rooted expectation that Moore’s Law improvements in CMOS semiconductor technology would continue unabated into the next century. Exploiting the potential of this IC technology, with the attendant increase in chip size, switching speed, and transistor density, necessitated significant improvements in packaging technology.
In the 1990’s, under the influence of growing product complexity, packaging evolved from an IC technology enabler to a primary electronic product/system differentiator, driven primarily by market application requirements. In this environment, it was the reduced cost per function, rather than merely expanded functionality, that provided the major technology development and execution challenges [NEMI, 1996].
The industry roadmaps recognized six distinct semiconductor product categories [SIA, 1994]: “Low Cost” (typically less than $300), “Hand Held” (typically less than $1000), “Cost/Performance” (less than $3000), “High Performance” (more than $3000), “Harsh Environments,” and memory components. Together these categories encompassed the majority of the product stream of the semiconductor industry.
It was assumed that the market requirements would determine the power, voltage, operating temperature, and chip junction temperature, as well as the package volume and footprint for each specific product category, while all other parameters were established by the appropriate physical relations. Thus, thermal packaging throughout the 1990’s was driven by distinct economic constraints, derived from these product “price points.”
In the “low-cost” product category, including disk drives, displays, micro-controllers, and video cassette recorders (VCR’s), in which only “incidental” cooling expenditures could be tolerated, thermal management rarely went beyond reliance on buoyancy-induced natural circulation of air. Similar constraints severely limited the options for the battery-operated “hand-held” products, including the personal digital assistants (PDA’s) and cellular phones, where clever use of heat spreaders generally made it possible to cool the 1-2W IC’s.
In this category, thermal management was thus in balance with the battery power available for extended operation. Natural convection cooling was also generally the rule for the memory devices. But when many such DRAM’s and/or SRAM’s, each typically dissipating 0.5W, were stacked together, or densely packed on a printed circuit board, forced convection was used to keep these devices from exceeding their allowable temperatures of approximately 100°C or higher.
During the 1990’s, the automotive category claimed the “harsh environment” mantle previously worn by “mil-spec” components that for some 30 years had been the mandated choice for military avionics. The elevated ambient temperatures “under the hood” and elsewhere in the vehicle made it necessary for automotive IC’s, dissipating 10-15W, to operate reliably at temperatures exceeding 150°C.
While a wide variety of heat spreading and air-cooling strategies for elevated chip temperature operation have been successfully implemented in this product category, development efforts have also addressed conventional temperature operation based on the use of refrigerated cold-plates.
Throughout the 1990’s, heat-sink-assisted, air cooling was the primary thermal packaging approach for the “Cost/Performance” category, which included both desktop and notebook computers. Thermal management of the microprocessors used in desktop computers often relied on clip-attached or adhesively-bonded extruded aluminum heat sinks, cooled by remotely located fans. But as the chip power rose towards 50W, thermal packaging for this product category required progressively more refined designs, as well as lower thermal resistance interface materials.
In an attempt to minimize the performance gap between notebook and desktop computers, fan-cooled heat sinks did begin to appear in notebook computers towards the end of the 1990’s. However, throughout much of this decade, battery power limitations made it necessary to harness naturally convecting air, circulating past low-fin heat sinks and heat pipes, as well as metal cases heated by spreading, to provide the requisite cooling for the 3-5W chips.
Under the influence of the market forces described above, thermal management of nearly all the products in the “High Performance” category devolved to the aggressive use of air cooling. By the end of the decade, a renaissance in thermal packaging produced heat sinks for high-end commercial workstations and servers that were routinely dissipating 60-70W [McMillan, R., 1998; Halfhill, T.R., 1998] using technology that was a natural outgrowth of the air-cooled multichip modules of the 1980’s.
However, to fully exploit the thermal potential of compact heat sinks – fabricated of bonded, forged, machined, or die-cast fins – it was necessary to prevent extensive “bypassing” of the air flow. This was accomplished by use of the so-called “fan-sinks” – where the fan was attached directly to the top of a pin- or plate-fin heat sink – or by integrating an air conduit (or duct) with the fan and heat sink design.
Over the Horizon
As the decade comes to a close, it is apparent that significant improvements in thermal packaging technology will be needed to cope with the anticipated surge in IC power dissipation to the 100-150W range predicted by the 1997 SIA Roadmap. The “rising tide” effect and anticipated introduction of far more powerful batteries for hand-held and portable electronics will necessitate enhanced cooling capability even at the lower margins of the power dissipation curve.
It is, nevertheless, clear that the 1990’s have left an indelible mark on the morphology of thermal packaging. While “price points” may shift, market-driven thermal packaging for advanced IC’s – as it emerged in the 1990’s – is no longer merely a “differentiator”; rather, it is essential for survival.
To facilitate ever shorter product development cycles, the de-coupling between thermal design and electrical design – achieved by the allocation of the chip backside to heat removal – is likely to continue. Similarly, it will be necessary to accelerate the industry-wide acceptance of thermal and thermofluid modeling software, so as to expand the simulation-based development and implementation of advanced packaging.
In keeping with the lessons learned from the marketplace, next generation thermal packaging solutions can be expected to continue to exploit the ambient air as the ultimate heat sink and use designs borrowed from the compact heat exchanger industry to achieve the requisite heat rejection density. A variety of techniques, from solid conduction to thermosyphon convection and from pumped liquid transport to vapor diffusion, can be expected to “spread” the heat to a finned surface and/or external “case.”
Nearly all the present thermal packaging solutions are constrained by the thermal resistance at the solid interfaces along the primary heat removal paths from the chip to the ambient air, notably at the chip surface and at the heat sink base. Although new materials and attachment techniques, introduced in the 1990’s, have substantially lowered these interfacial resistances, further improvements will be needed if thermally-induced failure rates and the unit costs of heat removal (c/W) are to decrease.
Alternatively, it is possible to both remove and transport the heat from the chip to the base of the heat sink or enclosure walls by use of a dielectric liquid, chosen for its chemical inertness and dielectric strength, as in the previous generation of supercomputers, such as the Cray-2, SS-1 and ETA-10.
Recent research has demonstrated that approximately 45W/cm2 [Watwe, A.A. and Bar-Cohen, A., 1997] can be removed with a quiescent perflourinated liquid in pool boiling and that spray evaporation with the same fluid can raise this limit to 60W/cm2 [Pautsch, G.W. and Bar-Cohen, A., 1999]. While these values would accommodate the peak heat fluxes anticipated in the SIA National Technology Roadmap 1997, current research is aimed at raising these limits even further to approximately 100W/cm2.
To maintain an invariant chip temperature, as the chip power dissipation increases, it is desirable to reduce the resistance between the chip and the ambient and/or decrease the local ambient temperature. A review of the five decade history of thermal packaging reveals that essentially all the effort and talent of the community has focused on reducing the resistance to the near total neglect of the “refrigeration” option.
As the 1990’s drew to an end, the propensity of CMOS for significant speed improvement with reduced temperature and the prodigious future heat removal requirements, have encouraged a growing number of product developers to more carefully explore this option, pioneered by Control Data Corporation in the early 1970’s [Doyle, M.A., et al 1973].
It may thus be expected that refrigerated computer systems, in a wide variety of configurations, will become more prevalent in the next decade. Commercial vapor compression systems, producing a stream of chilled air flowing past present-day heat sink designs, may be used to stabilize chip temperatures at the desired levels despite rapidly increasing power dissipation.
Alternatively, directed chilled air and/or refrigerated cold-plates could be used to provide chip operation at or below room temperature. Present trends suggest that such refrigerated cooling, already offered for high-end servers [Schmidt, R., 1999], will slowly migrate to the Cost/Performance product category.
As we near the millennial divide, world-wide sales of Cost/Performance and High-Performance computers are rapidly approaching 100 million units per year. The substantial material stream and energy consumption associated with the thermal packaging of these products, as well as other categories of computers and electronic equipment, make it necessary to bring the concepts of “design for sustainable development” to this most essential industry of the 21st century.
Far-sighted thermal packaging researchers have begun to explore the implications of entropy considerations on the design of electronic cooling systems [Ogiso, K., 1999]. However, the severe volumetric and areal heat generation rates, associated with future electronic products, militate against single-minded reliance on minimization of entropy generation in the coolant, based on “second-law analysis”.
Rather, it appears that for applications involving the high-performance, air cooled heat sinks, expected to dominate future applications, prime attention must be devoted to the minimization of heat-sink and heat-spreader mass. Several recent studies have shown that such “thermoeconomic” perspective can also achieve significant improvements in cost-effective heat sink design [e.g., Bar-Cohen, A. et al, 1998].
Closure
Thermal management has played a key role in the growth and maturation of the electronic industry during the second half of the 20th century. Many of the benefits associated with miniaturization and high reliability can be traced to continuous improvements in thermal packaging technology, thermal design and optimization tools, and the rapid implementation of new and novel thermal control techniques.
This brief review makes it apparent that significant advances in cooling techniques, heat transfer media, and thermofluid modeling tools will be needed to cope with the projected “Moore’s Law” surge in chip power dissipation. Perched on the millennial divide, the thermal packaging community is poised to face the challenges ahead with confidence; a confidence forged in past successes and informed by deep knowledge.
Let the chip developers, product managers, and system integrators – working to exploit the future generations of high power, high heat flux IC’s – know that we are prepared; so please “make our day!”
References:
1. Bar-Cohen, A.,1987, “Thermal Management of Air- and Liquid-Cooled Multichip Modules,” IEEE CHMT Transactions, CHMT-10/2, pp 159-175
2. Bar-Cohen, A., 1993, “Physical Design of Electronic Systems -Methodology, Technology Trends, and Future Challenges,” Chapter 1, in Advances in Thermal Modeling of Electronic Components and Systems – Vol 3, edited by A. Bar-Cohen and A.D. Kraus, ASME Press, pp 1-60
3. Bar-Cohen, A., Iyengar, M., Benjaafar, S., 1998, “Design for Manufacturability of Natural Convection Cooled Heat Sinks, Proceedings, Heat Exchangers for Sustainable Development, Lisbon, Portugal, June
4. Bergles, A.E., Chu, R.C., and Seely, J. H., 1972, “Survey of Heat Transfer Techniques Applied to Electronic Equipment,” ASME Publication, 72-WA/HT-39
5. Bergles, A.E. and Bar-Cohen, A, 1990, “Direct Liquid cooling of Microelectronic Components,” in Chapter 5, in Advances in Thermal Modeling of Electronic Components and Systems – Vol 2, edited by A. Bar-Cohen and A.D. Kraus, ASME Press, pp 233-342
6. Cockroft, J.D., 1925, “The Temperature Distribution in a Transformer or Other Laminated Core of Rectangular Cross-Section in which Heat is Generated at a Uniform Rate,” Proceedings of the Cambridge Philosophical Society, Vol 22, pp 759-772
7. Doyle, M.A., Cree, R.W., Keller, R., 1973, US patent 3,757,530
8. Danielson, R., Krajewski, N., Brost, J., 1986, “Cooling a Superfast Computer,” Electronic Packaging and Producton, Vol 26, No. 7, pp 44-45
9. Elenbaas, W., 1942, “Heat Distribution of Parallel Plates by Free Convection,” Physica, Vol 9, No. 1, pp 665-671
10. Halfhill, T.R., 1998, “Alpha 21264 Stakes Off The Claim Long Before Merced,” Digital Inc, Press release
11. Ing,P., Sperry, R., Philstrom, R., Claybaker, P., Webster, J., and Cress, S., 1993, “SS-1 Supercomputer Cooling,” Proceedings of the 1993 IEEE ECTC Conference, pp 219-237
12. Kaye, J., 1956, “Review of Industrial Applications of Heat Transfer to Electronics,” Proceedings IRE, Vol 44, pp 977-991
13. Lyman, J., 1982, “Special Report – Supercomputers Demand Innovation in Packaging and Cooling,” Electronics, September, 1982, pp 136-146
14. McMillan, R., 1998, “600+ MHz UltraSPARCIII Expected in Summer of 1998,” Sun World, Press release; Halfhill, T.R., 1998, “Alpha 21264 Stakes Off The Claim Long Before Merced,” Digital Inc, Press release
15. Moore, G.E., 1975, “Progress in Digital Integrated Electronics,” Proceedings of the IEEE International lectron devices Meeting, December, 1975, pp 11-1
16. Mouromtseff, I.E. and Koyanowski, H.N.,1935, “Analysis of Operation of Vacuum Tubes as Class C Amplifiers,” Proceedings of the IRE, Vol 23, pp 731-769]
17. Mouromtseff, I.E. ,1942, “Water and Forced Air Cooling of Vacuum Tubes,” Proceedings of the IRE, Vol 30, pp 190-205
18. Ogiso, K., 1999, “A Global Assessment of Coolability for Electronics Thermal design Based on Thermodynamic Aspects, ASME publication EEP-Vol 26-2, “Advances in Electronic Packaging,” eds Agonafer, Saka, Y.C. Lee, NY
19. Oktay, S., 1982, “Departure from Natural Convection in Low-Temperature Boiling Heat Transfer Encountered in Cooling Microelectronic LSI Devices,” in Heat Transfer 1982 – Proceedings of the 7th International Heat Transfer Conference, Vol 4, pp 113-118, Hemisphere Publishing, NY
20. Pautsch, G.W. and Bar-Cohen, A., 1999, “Thermal Management of Multichip Modules with Evaporative Spray Cooling,” Proceedings, ASME/IEEE InterPACK Conference
21. Schmidt, R., 1999, “Low Temperature Cooling of S-390 High End Processors,” Panel Session, ASME/IEEE InterPACK Conference, Maui, Hawaii
22. Tuckerman, D. and Pease, F., 1981, “High Performance Heat Sinking for VLSI,” IEEE Electron Device Letters, EDL-1, no. 5, pp 126-129
23. Vacca, A., Resnick, D., Frankel. D., Back, R., Kreilich, J., and Carlson, D., 1987, “A Cryogenically Cooled CMOS VLSI Supercomputer,” VLSI Systems Design, Vol 8, No. 7, pp 80-88
24. Watwe, A.A. and Bar-Cohen, A., 1997, “Enhancement of the Pool Boiling Critical Heat Flux Using a Binary Mixture of Dielectric Liquids,” Proceedings, Engineering Foundation Conference, Convective Flow and Pool Boiling, Irsee, Germany
25. Wu, P. and Little, W.A., 1984, “Measurement of the Heat Transfer Characteristics of Gas Flow in Fine Channel Heat Exchangers Used for Microminiature Refrigerators,” Cryogenics, Vol 24, pp 415-420
26. “The National Technology Roadmap 1992,” Semiconductor Industry Association, Washington, DC, 1992
27. “The National Technology Roadmap 1994,” Semiconductor Industry Association, Washington, DC, 1994
28. “National Electronics Manufacturing Technology Roadmaps,” National Electronics Manufacturing Initiative, Inc, Virginia, US, 1996
29. “The National Technology Roadmap for Semiconductors: Technology Needs – 1997 Edition,” Semiconductor Industry Association, Washington, DC, 1997
