Thermal conduction into a printed circuit board (PCB) is often an important part of the critical heat transfer path in electronic devices. Efficiently capturing the effect of the heterogeneous and anisotropic nature of the PCB’s copper distribution on local thermal resistance in a simulation has long been a goal of the electronics thermal analyst community. There are many modeling options available that offer simplicity at the expense of accuracy, and vice versa. The method discussed here may be viewed as a compromise between computational effort and achieved accuracy.
The least computationally intensive approaches are those that employ a global orthotropic material for the entire board. The values used for the orthotropic thermal conductivities range in the literature from semi-experimental formulations [1, 2] to thermal resistance network analytical derivations [3]. Using a single material property for a PCB is adequate for simulations that do not have the board on the critical heat transfer path, but the failure to capture the local effective thermal conductivity variation and heat spreading limits its usefulness in most other applications [4].
Methods that move the single material assumption to the layer scale have become common in applications concerning package characterization or design [5, 6, 7]. Using this approach, estimates are made based on copper content for the in-plane and through plane conductivities and a single material is used for each metallic and dielectric layer. This is an improvement over the single material method, but has questionable validity when the layer demonstrates strong non-uniformity in copper distribution. There have also been several methods introduced to consider local variations of thermal conductivity within the layer involving finite element and finite difference iterative calculations [8, 9].
The approach presented here also aims to refine the thermal conductivity description within the metallic and dielectric layers. An array of rectangular tiles, fitting together, without overlap (tessellated), is used to map the thermal conductivity distribution for all layers on a PCB based on monotone images exported from board layout tools. Structured pixel counting within the defined tiles, along with thermal resistance network theory, is used to estimate the local thermal conductivity values expeditiously, and with accuracy sufficient to produce results within engineering tolerances. This tiled thermal conductivity method is well suited to be applied to finite volume solutions, a popular method used to solve conjugate heat transfer problems in the electronics industry.
Creating a tessellated thermal conductivity map for a PCB is contingent upon the extraction of monotone images from the board layout tool for each metallic layer and the electrical vias. The black pixels in the images represent copper, and the white pixels represent dielectric material.
Each image is then reduced to a tiled array based on settings for:
Resolution of Longest Side: This setting controls the number of tiles to be used along the longest dimension of the PCB. A large number here indicates that a large number of tiles is desired in the resultant thermal conductivity map for this layer.
Number of %Cu Bands: Each tile created will be sorted into one of many pre-defined intervals of orthotropic (kx, ky, kz) thermal conductivity. This setting controls how many intervals (‘bands’) will be considered for kx, ky and kz, and thus controls the precision at which the thermal conductivities are computed.
THERMAL CONDUCTIVITY DERIVATION
Each tile will be assigned an orthotropic material property based on the characteristics of its corresponding image section. Figure 1 is an enlarged view of an individual tile from a metallic layer image.
A black pixel in this figure represents the conductor material and a white pixel represents the dielectric material. Each of the image tiles is analyzed to determine values for the in-plane thermal conductivities (kx, ky) and the through plane thermal conductivity (kz).
Figure 1. Enlarged view of an image section representing one tile.
The through plane conductivity (the z-direction in Figure 1) for a tile on a single layer is calculated by assuming that all the dielectric and conductor pixels in the image section are thermally in parallel.
Both in-plane conductivities are computed in a similar manner. For the x-direction, each horizontal row of pixels is assumed to be thermally in parallel. The thermal resistance of each horizontal row is calculated by assuming all pixels in that row are thermally in series.
For each row, the thermal resistance is:
Rrow = (Row White Pixel Count)•LPixel/[kDielectric•WPixel•tLayer] +
(Row Black Pixel Count)•LPixel/[kConductor•WPixel•tLayer]
The effective thermal conductivity in the x-direction is then:
1/Rtotal = Σ1/Rrow
kx = [LTile/(WTile•tLayer)]•[Σ1/Rrow]
The calculation for the y-direction is the same, but the pixel columns are used in the expressions above rather than the rows.
This procedure is followed for all defined tiles to create the thermal conductivity map of the layer. A three dimensional, orthotropic thermal conductivity mapping of the entire board is created by repeating this approach for all metallic and dielectric layers.
VALIDATION
To confirm the quality of the approximations made in this approach, the technique of using detailed simulations to numerically generate data points for comparison purposes was employed. Explicit models of a single layer board with traces included in several typical orientations and a single footprint heat source were created and compared with corresponding 10×10 tiled thermal conductivity map approximations. The average discrepancy in component temperature was recorded as 3.3%, with a maximum discrepancy of 15.3%. A complete description of these test cases and results is available in [13].
Figure 2. One of the images extracted from the layout tool and the resultant tessellated thermal conductivity map with these settings.
For further validation, this approach was also applied to a PCB for which empirical temperature data was available. The experiment consisted of an automotive board cooled via natural convection and radiation and is described fully in [13].
All of the components with significant dissipated heat load on the board were included in the analysis model as 2-R models, the best thermal representation available. The dissipated heat loads were taken from experimental measurements or from calculations where measurements were difficult. The PCB was modeled using the layer stack up and thickness for the design, along with tiled thermal conductivity maps for all of the layers. Each thermal conductivity map was created with identical image processing settings:
Resolution of Longest Side: 75
Number of %Cu Bands: 256
Figure 2 shows one of the images extracted from the layout tool and the resultant tessellated thermal conductivity map with these settings.
The PCB model was positioned in a simulated replica of the test environment and solved. Both measured and predicted case temperatures for the 2-R components are shown in Figure 3. The average level of discrepancy was 5.7%. This is an excellent level of correlation, well within typical accuracy expectations [12] for 2-R component models, and matching well with the deviations observed in the detailed simulation validation exercise.
TESSELLATION SETTING SENSITIVITY
An important practice in the field of computational fluid dynamics is verifying that the solution is mesh independent, i.e., additional computational mesh cells will not result in a gain in accuracy. An analog to grid independent solutions exists when utilizing this method to capture local thermal conductivity variations. The tessellation resolution must reach sufficient granularity such that the thermal conductivity mapping procedure no longer influences the predicted results.
To determine how sensitive the previous results are to the ‘Resolution of Longest Side’ and ‘Number of %Cu Bands’ settings a Design of Experiments [10] set was constructed and solved using the previous model as the baseline case. Six parameters were identified for study:
Resolution of Longest Side for
-Internal Layers
-External Layers
-Vias
Number of %Cu bands
-Internal Layers
-External Layers
-Vias
The range chosen for all of the ‘Resolution of Longest Side’ parameters is 1-75 (the upper limit of 75 matches the settings of the baseline results to which the forthcoming sensitivity data will be compared). The ‘Number of %Cu Bands’ doesn’t have a range per se, but rather a series of discrete options. The options considered for this study were: 256, 129, 65, 33, and 17.
Response surfaces [11] that yield expressions explicitly stating each component’s case temperature as a function of the six design parameters and expected confidence levels were created. These response surfaces were then used to investigate the sensitivity of the thermal results to tessellation settings. The full set of results is presented in [13].
The metallic layer processing results indicate that a moderate level of resolution is able to attain results within 5% of the baseline temperatures.The requirements ranged from 25-50 for the components investigated. This range translates to a tile dimension range of 6.8 -13.6 mm. While these dimensions do not correlate with any component dimension, it qualitatively is the point where most copper features are identifiable in a bulk sense despite the image tessellation occurring. The choice of %Cu bands was relatively unimportant in most cases. It is expected that this quantity could be much more critical for metallic layers with smaller amounts of copper however.
The vias processing results indicate that the choice of %Cu bands is more important than using a high level of resolution. A modest resolution selection (5-10) with the maximum 256 %Cu bands is appropriate for this application.
Figure 3. Predicted and measured case temperatures.
CONCLUSIONS
A tiled thermal conductivity map derived with structured pixel counting from monotone images representing the copper and dielectric distribution on the layers of a PCB was shown to correlate well with explicit, detailed trace simulations and with experimental data.
The temperatures predicted with this approach are dependant upon the settings used to describe the tessellation geometry. The sensitivity results presented [13] suggest that a tessellation resolution point exists where increasing the granularity of the tiled thermal conductivity map no longer influences the simulation results. For the PCB considered in the Validation section, tessellation independent results are achieved with modest settings for resolution of all layers and maintaining a high setting for %Cu bands. It is expected that tessellation independent status would be achieved at different settings for boards and layers with lesser amounts of copper.
ACKNOWLEDGEMENTS
The author wishes to thank Sam Gustafson of Johnson Controls for the provision of the experimental data referenced here.
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