HARSH ENVIRONMENT ELECTRONICS
Harsh Environment Electronics are the unique electronic systems that operate our flights, factories and autonomous vehicles in a safe and reliable manner. As these systems manage the safety of persons and/or vehicles that cost millions of dollars, strict hardware and software system standards have been developed to operate in their harsh environments. For example, class I avionics need to operate in a continuous ambient environment of -54°C to 55°C and a temporary 30-minute free convection ambient environment of 71°C. Given that chip junction limits are typically 95°C to 105°C, it is clear that the thermal budget for the thermal designer for these applications is minimal.
LRU electronics
Because of the limited thermal budget, rugged embedded electronics typically rely on heat removal from the top of the chip packages, where heat is removed through the thermal interface material (TIM) to the heat spreader as illustrated in Figure 1 for a typical line replaceable unit(LRU).
HETEROGENOUS INTEGRATION FOR HARSH ENVIRONMENTS
Heterogenous Integration is often described as “packaging technology to integrate dissimilar chips with different functions” [1]. Heterogenous Integration of components is intended to lower power consumption, footprint, development time, and cost while decreasing latency compared to conventional single chip integration approaches [2].
As heterogenous integration uses silicon as the interposer, it also allows for further integration of silicon photonics. Silicon photonic components such as optical, laser diodes, waveguides, modulators, and detectors yield the promise to further advance bandwidth and achieve ultra-low latency. Urino et al. [3] describes this in a concept called “server on a chip” as depicted in Figure 2.
In this concept of an on-chip server, dissimilar components are combined onto a single integrated chip, performing all the basic functions of a server, effectively operating as single chip system located on the silicon. This effectively transitions the role of the traditional multi-layer PCB to that of mechanical support and power and I/O management as platform as most of the data communication is managed on the silicon interposer.
When evaluating how heterogenous integrated packages can be applied in for harsh environments, select technology innovation area needs can be identified.
3D THERMAL INTERFACE THERMAL TECHNOLOGY
As stated, rugged harsh environment electronics rely pre-dominantly on chip top-side heat rejection through a thermal interface layer and a heat spreader mounted over the flip-chip package. This thermal interface layer serves to thermally connect components of dissimilar coefficient of thermal expansion (CTE) such as silicon(chip) and aluminum or copper(heat spreader). As ruggedized electronics typically get produced in moderate volumes (100s-1000s), chip height, chip warpage and other non- planarity can be a challenge. The thermal interface material also serves to compliantly compensate for these differences by filling gaps and ensuring good thermal contact between these components.
As heterogenous integration introduces 3D non-planar and large silicon structures, challenges can be envisioned to connect a top-side heat sink using current thermal interface materials. It can also be expected that as multiple micro-ball grid array connections are used to create vertical stacks, height and planarity variations will accumulate resulting in amplified variance in the eventual location of the top-side chip interface as illustrated in Figure 3.
Kirk et al. [4] developed a novel thermal interface method that connects to the chip after assembly by using a controlled spring loaded expansion that occurs during a low temperature re-flow process as illustrated in Figure 4. The novel insight used by this method is the use of low melt point (LMP), high thermal conductivity solders such as Indium contained in thin flexible high temperature polymer foil like urethane. As select polymers have a melting point higher than that of LMP solders, they can successfully retain a solder in liquid state and “freeze” when the solder re-solidifies. In this concept, the connector is attached to the heat spreader in a state where the spring is compressed.
The system is then assembled over the chip with some thermal grease on the chip in step 1. In step 2, the LMP solder melt point is exceeded during a brief re-flow, allowing for the spring to expand and lower a copper heat spreader down to the chip interface, compressing the thermal grease. Finally after cool-down, the heat connector is frozen in state that is matched with the height and angle variation of the chip. Further variations of this technology can be envisioned, where not one, but multiple tiles press down to follow the contour of 3D heterogenous chip topology.
In variant of this concept, a thermal interface material system by de Bock et al. describes a thermal interface system that uses a thicker layer of LMP solder, encapsulated by an ultra-thin layer micro layer of a high temperature polymer [5]. When pressure is applied during heating, the LMP solder flows conformal to the chip shape while being contained by the thin polymer “bag” as illustrated in Figure 5. When the containment layer polymer is sufficiently thin, its detrimental contribution to the TIM thermal resistance can be sufficiently small, outweighed by the superior thermal conductivity of LMP solders like Indium(k ~ 70 W/m-K), which exceeds common thermal interface materials.
conform to 3D chip topology [5]
The benefits of this concept are similar to the aforementioned flexible metallic heat connector as in compensating for chip height and angle variation, but in addition, non-planar chip warpage and 3D topologies can potentially also be managed. As LMP solder never comes in full contact with the silicon chip, no inter-metallics are formed, eliminating the need for barrier coatings and allowing for re-workability.
SEMICONDUCTOR CTE MATCHED HEAT SPREADERS
As 3D stack-ups can contain multiple layers of heat generating components, managing hot-spots can be increasingly challenging. Heterogenous integrated architectures hotspots will likely occur in the layers furthest away from heat sinks such as the PCB and the top-side of the chip.
A semiconductor CTE matched heat spreader embedded in the 3D package as illustrated in Figure 6 can bring heat out from the center of the 3D stack-up to the periphery where a TIM or via based solution can be used to remove heat. These dedicated heat spreader layers would require electrical pass through to allow for connections from the interposer to the top-side chips. Minimizing thermal stress and warpage is also important as electronics used in harsh environments experience extreme thermal transients. Therefore, a heat spreader-silicon CTE match is preferred.
The Defense Advanced Research Project Agency’s (DARPA’s) thermal ground plane (TGP) program led to the development of a variety of semiconductor matched heat spreaders [6] (Figure 7). These heat spreaders are effectively two-phase vapor chambers designed for operation in high-g environments.
from A. Bar-Cohen et al. [6]
Materials such as Silicon [7], CuMo [8], Kapton [9] and AlN [10] were evaluated as vapor chamber vessels by a variety of teams under this program. By development of two-phase evaporator and condenser zones, it was demonstrated that effective thermal conductivities could be achieved that greatly exceeded the inherent vessel thermal conductivity, even in the presence of adverse g-forces [10]. Likely through re-development of this TGP concept, novel versions can be developed to address hot-spot mitigation needs for heterogenous integrated packages.
ACTIVE TRANSIENT HOT SPOT THERMAL MANAGEMENT
Another way to manage local hot spots is by providing active in-package hotspot mitigation. Especially when 3D heat rejection is considered, moving heat from an embedded chip layer to another that has top-side cooling can be advantageous. Bar-Cohen and Wang pioneered in-package thermoelectrics extensively enabling several degrees hot-spot cooling [11].
Further work from Green and Fedorov et al. [12] further explored the use of in-package micro-thermoelectrics and thermal energy storage technology, allowing for novel transient thermal management approaches for management of hotspots internal to 3D packages as shown in Figure 8. As thermoelectrics are effectively heat pumps, they can also be used to manage mechanical stresses by providing heat or cooling to select areas of a 3D package to counter any thermal gradients produced by the electronic loading of the chipsets.
Such technologies can especially be effective in enabling on-package silicon photonics as optical components require temperature stability and/or temperature control near the temperature sensitive components such that the laser diodes and detectors do not experience any lasing wavelength shifts.
CONCLUSION
Heterogenous Integration is an integration technique offering the combination of dissimilar components onto a 3D package. Several technical challenges in the application of Heterogenous Integration for harsh environment electronics exist. Expanded temperature range operation, extreme hot and cold operation, severe mechanical requirements and minimized thermal budgets are examples of requirements that illustrate the challenges of developing thermal solutions for harsh environments.
As with most electronics lifecycles, operation of new technology often starts in highly competitive applications with limited operational life, of which some can be consumer electronics. As these technologies mature and gain more pedigree, more and more application for critical electronics in harsh environment can be considered. The study identified three areas of technology research that can be focused on to further accelerate this progression. These are, the development of 3D thermal interface technology, application of CTE matched heat spreaders and active transient thermal hotspot management. It is anticipated that with time and development support, these technologies will further advance allowing one day for safe and reliable operation of heterogeneously integrated electronics in the aerospace, industrial and other safety critical harsh environment electronics systems of tomorrow.
