A common enough question. Heatsinks are often perceived to be the magic answer to all electronics cooling challenges. They should be called ‘area extenders’ as heat does not just disappear into them. Heat spreads throughout a heatsink passing to the air over a much larger area than it would otherwise do. Air can then do its magic, whisking the heat away thus keeping … [Read more...]
Experiment vs. Simulation, Part 5: Detailed IC Package Model Calibration Methodology
In the royal family of thermal IC package modelling types, a detailed model is King. All critical 3D geometry is modelled explicitly, no abstraction into a thermal resistor equivalent model, no hiding all the proprietary design information inside either. Pros and cons of detailed models I covered a few years ago in this blog. Packaged ICs are complex, constructed of many parts, … [Read more...]
Experiment vs. Simulation, Part 4: Compact Thermal Models
Electronics cooling simulation was born out of the world of CFD, rather fully conjugate heat transfer simulation where convective, radiative and conductive affects are considered concurrently. Back in the day much talk was had about turbulence modelling, convective discretisation schemes and linear equation solvers, all typical CFD subjects but somewhat out of place in the … [Read more...]
CFD – Colourful Friday Distractions
By way of an apology for the more verbose blogs I’ve been issuing recently I’d like to present you with a blog that serves no other purpose than to show a pretty picture. CFD as an acronym has quite a few different interpretations. Contracts for Difference if you’re into your financials. Colour For Directors if you’re in marketing. Cheats, Frauds and … [Read more...]
Measured Thermal Resistance of Microbumps in 3D Chip Stacks
Evan Colgan, Jamil Wakil, IBM Introduction As it becomes increasingly difficult to scale devices down to improve performance, alternate approaches such as 3D chip stacks are being developed, which improve system performance by increasing the interconnect density and reducing the interconnect length(1). The stacking of multiple chips with through silicon vias (TSV) and fine … [Read more...]
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